I’ve a question about performance results of different counters in your book. Can you elaborate why the performance of LFSR counter is slower than the binary.

Hi Divya,

The reason is that there is a comparator on the output of the LFSR. Without the comparator, LFRS counter becomes a shift register and will have a higher performance.

Thanks,
Evgeni

A link to German FPGA news site with a comment on the book: http://www.fpga-news.de/2011/06/neues-aus-der-fpga-welt-23/
Here is the link translating the page into English

Evgeni,

can you explain a bit more why “asynchronous reset nets usually have more relaxed timing constraints comparing to the synchronous reset”?

Thanks for the great book!

Guy.

Guy,

Designers that use asynchronous resets are usually less concerned that all the registers come out of reset in the same clock. If they were, they would use synchronous reset instead.

For that reason there is no point to apply tight timing constraints to asynchronous reset nets. In fact, asynchronous reset nets don’t even participate in the timing analysis by default. You need to add “ENABLE=reg_sr_o” and “ENABLE=reg_sr_r” constraints (Xilinx UCF format) to do so (the default is different for Xilinx V6/S6 comparing to earlier architectures). And even if you do want to constrain async reset nets, none of the constraints – FROM-TO, MAXDELAY, etc. (Xilinx UCF format) – can guarantee minimum delay, only the maximum. That’s important, because in large designs with high-fanout async reset nets, routing delays can reach several ns, and the difference between longest and shortest reset net can exceed a clock period.

Thanks,
Evgeni

I see what you mean. It’s not the asynchronous nature of the reset that makes it more relaxed, it’s just that it isn’t usually included in the static timing analysis. That’s a good point.

In some FPGA technologies – like Spartan-6 – it’s also technically possible, although not recommended, to use a global clock network to distribute a global reset signal. Do you have any experience with that?

Cheers,
Guy.

Guy,

Low-skew clock networks can be used not only for resets, but for high-fanout control signals. I’ve successfully used clock enables routed as global clocks in large pipelines.

Thanks,
Evgeni

Here is a review of the book in EETimes

plz. provide the source codes in vhdl too.

Unfortunately, VHDL code is not available, only Verilog. Most of the examples are simple enough, and you might want to consider using Verilog to VHDL converters.

Evgeni

Evgeni,

what max working frequency have u achieved in your practice?

What is best result?

Thank you.

Hi Alexey,

I worked with designs where small parts are running at a frequency close to the maximum supported by that particular FPGA: 500-550MHz. On average (if it’s correct to apply it in this context), I deal with 200-250MHz frequencies.

Thanks,
Evgeni

Where can I buy your book in india.. I can only pay in indian currency.

Hi,

Ok, let’s figure that out. A few questions:
Are you interested in paperback or electronic version ? Can you pay with PayPal ? What websites are you using to buy books/other products ?

Thanks,
Evgeni

Hi,

I generally use http://www.flipkart.com for any online purchase. Many other verilog books are listed there. I would love to have a paperback version. A proper paperback version not a scanned one.

Thanks

@Evegeni

Nothing like making your book available on flipkart. Most of the people here use the same site fo online purchase because of free shipment and assured genuineness. I feel it will the best plateform if u want to launch your book in a country like india where design and development work is on its all time high.
I do not have a paypal account.. 🙁

A reader has asked about ASIC gates to Virtex-6 logic cells conversion on page 187: 1 logic cell = 15 ASIC gates.
The first “official” mentioning of Xilinx logic cell to ASIC gate conversion is in Xilinx Zynq-7000 product brief: http://www.xilinx.com/publications/prod_mktg/zynq7000/Product-Brief.pdf , note 3 on page 2. This number is close to what I’ve seen in ASIC emulation projects using Virtex-5 and Virtex-6 devices.

hi sir..
could implement the all microprocessor architecture in fpga???

Hi,

Tip #65 in the book discusses some of the processor architectures supported in Xilinx FPGAs – either soft cores or embedded.

Thanks,
Evgeni

A reader pointed out the following error. In Tip #36 “FPGA CONFIGURATION” on page 179, the configuration time formula should read:
Config time = bitstream size / ( clock frequency * data width )

And yet another comment from a reader. On page 69 in “Inferring Register” section, the code for a register with both sync and async resets should be as follows:

always @( posedge clk , posedge areset)
if( areset )
dout <= 1'b1; else if( sreset ) dout <= 1'b0; else dout <= din;

Hi Evgeni,

in Tip #22, when computing the MTBF for a clock-domain crossing, where do you get the values for the T0, T and tau parameters from?

Thanks,
Guy.

Hi Guy,

I discussed the MTBF formula with an engineer knowledgeable in the subject matter. T0,T, and tau are an example, and don’t necessarily relate to Xilinx FPGAs characteristics.

Thanks,
Evgeni

@Evgeni I just posted the question on a Xilinx forum (http://forums.xilinx.com/t5/Spartan-Family-FPGAs/Synchronizer-Mean-Time-Between-Failure-MTBF-Estimation/td-p/178822) — let’s see if we can get an answer there.

Thanks,
Guy.

I’ve just received my book, I’m so excited! content looks better than expected 🙂

The book is available on flipkart.com for readers based in India.

@vipin
where to get an electronic version of the book ?

Hi,

There are three options to gen an electronic version: Amazon Kindle, Barnes & Noble Nook, and Google eBook. Kindle and Nook versions can be read on a PC, just like PDF.

Thanks,
Evgeni

Hi Evgeni,

I read about the primitive component CCGLUT5 in section 80 of the book. Can you provide more detail on the example with the pattern_matcher.

Are their other uses for this component? How does the tools leverage this component in synthesis optimization or another manner, then how does it do so? Any help would be appreciated.

Thank you in advance,

Hi Vincent,

The idea is to reconfigure LUT with a pattern using CFGLUT5 primitive instead of a more “traditional” approach of storing mask, match, and data in registers and use regular LUTs to do comparison. That way the circuit uses much less logic resources.

CFGLUT5 is a fairly new Xilinx primitive that became available starting from Virtex-5 chips. As far as I know, current synthesis and p&r tools don’t automatically infer it, if that’s what you’re asking. And it’s not a trivial thing to do, because of the way the primitive is programmed.

Another use of this primitive could be a small re-programmable ROM.

Thanks,
Evgeni

Hi Evgeni,

Thank you for your reply. I looked into the example further. I have a few questions which I hope you can answer or guide me to the solution:

1- Example 2 has a one-bit output. Example 1 using the CFGLUT5 has a 32-bit output. Would we need additional LUTs to reduce the output to one-bit?

2- To load the CFGLUT5, would we need 32 CLK cycles? If so, the trade-off between the examples is speed vs. area?

3- This is a minor note, but I calculate 240 flip flops (not 180). Did I miss something?

Thanks again for the book… soo much knowledge 😉

Hi Vincent,

You’re right about 1 and 2. But even with LUTs to reduce to 1-bit output, CFGLUT5 utilizes less area.
Data, data mask, and pattern match require 80 registers each. So it’s 180 in total. You can look into pattern_match.v RTL and its MAP report in the accompanied source code.

Thanks,
Evgeni

hello everyone,

I am a new learner for this book. so all are help me for any doubts. Thank u.

Just got the book … it looks awesome.

Is there a consolidated errata ready for download that I can printout and keep with the book?

Thanks!
Rick

Hi Rick,

There isn’t much errata, and it’s all in the comments

Thanks,
Evgeni

Hai,
I am trying to implement ping-pong(dual) buffer…. can u help me out..

Dear Evgeni
I have some experience in FPGA design with vhdl but now I want to start designing with SystemC and Xilinx’s FPGA.
Which tools do you offer and you think they lead to approperiate practical results in Xilinx’s FPGAs.

thanks,
hewraz.

Hi Hewraz,

Xilinx tools – ISE, Vivado – are good for whatever you want to do.

Thanks,
Evgeni

Hi Evgeni !

I am interested in getting an e-book version. However, this seems not applicable in South Asia (Singapore).. Please guide me on how to get an e-version in Singapore!

Thanks !

Hi Ash,

There are three options to get an electronic version: Amazon, Barnes & Noble, or Google Books.
One or more of those options must be working in Singapore.

Thanks,
Evgeni

Hi Evgeni,

Could you give me a free book copy, as I will teach a MSc. Level FPGA module in 2013 spring? I’m happy to include your book in the reading list of the course.

Regards,

David

Hi David,

Is soft copy ok (kindle or PDF format), or you want a paperback ?

Thanks,
Evgeni

Hi,

1. The short answer: the same way as regular modules. IP cores can be packaged as a Verilog/VHDL source code, post-synthesis netlist, be encrypted or not.
2. Using a custom bridge logic

Thanks,
Evgeni

regarding Microblaze processor, various interfaces (DPLB: Data interface, Processor Local Bus
DOPB: Data interface, On-chip Peripheral Bus
DLMB: Data interface, Local Memory Bus (BRAM only)
IPLB: Instruction interface, Processor Local Bus
IOPB: Instruction interface, On-chip Peripheral Bus
ILMB: Instruction interface, Local Memory Bus (BRAM only))
can u please give a brief info. of these?

i want to use FPGA as switch in controlling the speed of induction motor and need help

i want to use FPGA with decoder.that decoder may be connected with RF receiver.i want the working of FpGA with that above components

Hi,

Whether you can use FPGA or not depends on the interface of that RF receiver chip.

Thanks,
Evgeni

Hello Evgeni,
Can you mail me e-book must be in PDF format on my mail(shilankarnilesh09@gmail.com)?

Hi Nilesh,

Thanks for the interest in my book. The book can be only purchased either in paperback or kindle formats.

Evgeni