LFSR Counters
Most of the EE or CS graduates know or at least have heard about different types of hardware counters: prescaled, Johnson, ripple carry, linear feedback shift register (LFSR), and others.
The majority of logic designers use the first two types, because they’re simple to implement in Verilog or VHDL. However, for some applications LFSR counters offer a significant advantage in terms of logic utilization and maximum frequency.
The other day I run into Xilinx LFSR Counter core and decided to explore its advantages. I was so impressed with its area saving comparing with regular counters that I decided to write an online tool that generates a Verilog code for an LFSR counter of an arbitrary value.
This LFSR Counter Generator tool is running on the server. The time it takes to generate the code depends exponentially on the counter size. It takes several seconds to generate a 20-bit counter. But bigger counters cause the server to timeout with the current tool implementation.
I’m planning to tweak the implementation to be able to generate counters up to ~30 bits. More than that would take too long no matter what approach is taken.
Please post you comments about the experience with the tool, features you’d like to add, and the issues you’ve seen.
References:
- Peter Alfke, Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators,
Xilinx application note Xapp052 - Maria George and Peter Alfke, Linear Feedback Shift Registers in Virtex Devices, Xilinx application note Xapp210
- Xilinx Linear Feedback Shift Register (LFSR) Logic Core
Are you planning to add VHDL support as well
Hi Yulya.
I’ve added VHDL support. Please give it a try and let me know if that’s what you wanted.
Hi
i am a engineering student who likes verilog and vhdl coding a much….. i have one international papers published….. Now i need to know how to give constraints to a verilog model ….. i need both area and timing constraints…. i am using xylinx sparten 2 xst200 pq208..
thank’s and regards
yajnesh padiyar
Hi Yajnesh,
The best source to understand timing and area constraints is Xilinx Constraints Guide document.
Thanks,
Evgeni
Hi Evgeni
thank you very much for your advice
Evgeni,
I like it very much. Good stuff.
Now, we can have only one count #. Can you generate lfsr_done for each count # ?
Let’s say I want to have output of count = 8, 16 and 64.
If the code can generate, lfsr_done0 (count =8), lfsr_done1 (count =16) and lfsr_done2(count =64), that would be very helpful. Of course, count numbers would be user defined.
//Cliff
Hi Cliff,
Because an LFSR counter is using a pseudo-random sequence to count, it wouldn’t be possible to “embed” multiple count values in one.
A potential solution would be to chain multiple counters, so that lfsr_done triggers the next one up in the chain.
In your case you might chain three counters – 8,8, and 48 – to achieve counting 8, 16, and 64.
But for small counters the advantage of LFSR over a regular counter in terms of space is less significant.
Thanks,
Evgeni
Hi Cliff,
With the LFSR Counter Gen I can generate a LFSR with loadable input ?
Best regards,
Alex
hi, the LFSR counter generator that i downloaded can’t be install, can i know what is the problem and can tell me the way to install?
Hi,
It doesn’t require any installation – it’s just an executable. Do you have any error message? Can you try compiling the program yourself and run it?
Thanks,
Evgeni
when i click on the .exe, the small black windows disappear immediately. So, what is the problem?
Hi,
It’s a command-line, not GUI application. You need to open it from shell/command line prompt.
Thanks,
Evgeni
Hi,
assign lfsr_equal = (lfsr == 14′h2000)
Is it the lfsr value can be any number?
What will happen if the lfsr is not 14′h2000, for exp: lfsr == 14h’600?
Best regards,
Policeman
Hi,
No, a generic LFSR cannot reach any value. Only those LFSRs with so called “maximum length” property can. The LFSRs I use to generate counters do have this property.
LFSR sequence is pseudo-random. So (lfsr == 14′h2000) doesn’t mean that the next value is h2001 or h1FFF. The same goes with 14h’600. What is guaranteed is that each value LFSR visits is unique, but not the sequence.
Thanks,
Evgeni