reg [4:0] crc_iteration;

reg [4:0] crc;

reg [3:0] data;

integer i;

reg [4:0] N_in;

initial begin

begin

for(N_in=0; N_in < 4;N_in=N_in+1) begin

for(i=0; i<4; i=i+1) begin

crc_iteration = crc5_serial(N_in,0);

end

$display("*********** CRC_ITERATION VALUE *************: %b",crc_iteration);

end

end

#100;

$finish();

end

function [4:0] crc5_serial;

input [4:0] crc;

input data;

begin

crc5_serial[0] = crc[4] ^ data;

crc5_serial[1] = crc[0];

crc5_serial[2] = crc[1] ^ crc[4] ^ data;

crc5_serial[3] = crc[2];

crc5_serial[4] = crc[3];

end

endfunction

Output:

# KERNEL: *********** CRC_ITERATION VALUE *************: 00000

# KERNEL: *********** CRC_ITERATION VALUE *************: 00010

# KERNEL: *********** CRC_ITERATION VALUE *************: 00100

# KERNEL: *********** CRC_ITERATION VALUE *************: 00110

There are multiple ways of handling misaligned data ends. Padding with zeros is not one of them.

One simple way is to have separate CRC circuits handling any possible case of misalignment, for example 8,16,…56bit.

Thanks,

Evgeni

i am padding with 0s, which i assume should be a dont care for CRC, right? but the result mismatches. ]]>

thanks reversing the bits helped. ]]>

I’d say most of the times the issue is with correct bit ordering of the data into parallel CRC. Try to invert 64 bits (such that bit[0] becomes bit[63], etc.)

Thanks,

Evgeni

1. LFSR is all initialzed to 0s.

2. 64 bit data width, 11 bit CRC.

3. Tried simple data case 0×0000_0000_0000_0001 and the output matches in this case. which is 0×621 the polynomial itself.

I am lost as to what the problem could be. Any help is appreciated. It is kind of urgent.

]]>Most of the problems with parallel CRCs are related to data ordering. I presume that serial CRC (when you feed one bit of data at a time) and 32-bit CRC (when you feed one DWORD of data at a time) are working.

If there is a mismatch in 128-bit CRC, one possibility is that 4 DWORDs of data are not ordered correctly (for example dw 0,1,2,3 vs. dw 3,2,1,0).

Another possibility is data misalignment. If your data doesn’t end at 128-bit boundary, you cannot include trailing zeros in 128-bit CRC calculation. There are several methods how to handle CRC checking of misaligned data.

Thanks,

Evgeni