Comments for OutputLogic.com

Comment on Parallel CRC Generator by Evgeni

Evgeni — Thu, 02 Sep 2010 19:13:59 +0000

Hi Vikram,

There is a long list of things that can go wrong during CRC calculation. I’d need more information to help you.

Thanks,
Evgeni

Comment on Parallel CRC Generator by vikram

vikram — Thu, 02 Sep 2010 08:50:30 +0000

i am giving a date packet but not able to see the correct crc

Comment on Parallel CRC Generator by vikram

vikram — Tue, 31 Aug 2010 10:14:21 +0000

Hi,
I am working on CRC 32 bit project which has 120 bit or 15 byte data as serial in stream coming on an ethernet cable on the receiver side.i have the program and am not able to see the right crc in the simulation.i saw the program on your site but seems to long to get the crc32.the logic is as below:

ENTITY TL_CRC_32 IS

PORT (
clk : IN STD_LOGIC; — clock
reset : IN STD_LOGIC; — asynchronous reset
crc32_init : IN STD_LOGIC; — set CRC register to initial value
crc32_enable : IN STD_LOGIC; — enable CRC calculation
serial_IN : IN STD_LOGIC; — serial input data
crc32 : OUT bus32); — CRC32 accumolator

END ENTITY TL_CRC_32;

ARCHITECTURE behaviour OF TL_CRC_32 IS

SIGNAL crc32_shifter : STD_LOGIC_VECTOR (31 DOWNTO 0);
–SIGNAL temp : STD_LOGIC_VECTOR (31 DOWNTO 0);
SUBTYPE poly_vector IS BIT_VECTOR (31 DOWNTO 0);
CONSTANT poly : poly_vector := X”04C11DB7″; — polynominal
CONSTANT initval : STD_LOGIC := ‘1′; — initial crc reg. value

BEGIN

shift_data : PROCESS (clk, reset) IS
BEGIN
IF reset = ‘0′ THEN
crc32_shifter initval);
ELSIF clk’EVENT AND clk = ‘1′ THEN
IF crc32_init = ‘1′ THEN — load crc reg with init value
crc32_shifter initval);
ELSIF (crc32_enable = ‘1′) THEN — serial crc bit calculation
FOR i IN 0 TO 31 LOOP
IF (poly(i) = ‘1′) THEN
IF (i = 0) THEN
crc32_shifter(0) <= serial_IN XOR crc32_shifter(31);
ELSE
crc32_shifter(i) <= crc32_shifter(i-1) XOR serial_IN XOR crc32_shifter(31);
END IF;
ELSE
crc32_shifter(i) <= crc32_shifter(i-1);
END IF;
END LOOP;
END IF;
END IF;
END PROCESS shift_data;

crc32 <= crc32_shifter;

END ARCHITECTURE behaviour;

Can you please help me?

Comment on Parallel Scrambler Generator by Jordy

Jordy — Mon, 16 Aug 2010 08:43:56 +0000

@Jordy
I’m sorry for my mistake,
you are right, it means hold the value for next scram_en valid.
thank you

Comment on Parallel Scrambler Generator by Jordy

Jordy — Mon, 16 Aug 2010 08:21:46 +0000

Hi Evgeni,
at your generated code “data_out <= scram_en ? data_c : data_out;"
why I think it should be "data_out <= scram_en ? data_c : data_in;"
in your code if scram_en == 0, then data_out <= data_out;
this code can never work, data_out will be always the reset value…
thank you

Comment on Parallel Scrambler Generator by Evgeni

Evgeni — Mon, 02 Aug 2010 16:41:05 +0000

Hi Ashok,

There are several ways to generate the code. I just picked this one as the most “basic”. As for the generate statements, it’s specific to Verilog-2001, and many developers are still using ‘95.
I guess having different options for the code generation will be a nice feature.

Also, using generate will result in less efficient code, at least for FPGA tools. I discuss it a bit in my Circuit Cellar article

Thanks,
Evgeni

Comment on Parallel Scrambler Generator by Ashok

Ashok — Mon, 02 Aug 2010 04:12:40 +0000

Why don’t you use variables and generate statement… It will be easier to read and very few lines…

Comment on Comments by Evgeni

Evgeni — Wed, 23 Jun 2010 15:47:20 +0000

You can have, for example:
data_out < = scram_en ? {data_in[15:8], data_c[7:0]}: data_out);

Comment on Comments by Martin

Martin — Tue, 22 Jun 2010 14:02:41 +0000

Hello Evgeni,
thank you for the hint,
it looks that with pass through the input will lead to the output and the lfsr_q will stall.
But how to pass through the upper 8 bits of a 16 bit bus while scrambling the lower ones or vice versa?
In this way IMO when the upper bits are used only these bits must be XORed to the lfsr and based on which or both bytes are passed through there should be 3 different lfsr_c vectors which are used to update the lfsr_q at the next clock edge.
Or is it much simpler but I haven’t recognized it?

BR, Martin

Comment on Comments by Evgeni

Evgeni — Mon, 14 Jun 2010 16:23:52 +0000

Hi Martin,

You can add pass_thru input, and change the logic to:

data_out < = pass_thru ? data_in : (scram_en ? data_c : data_out);

You'd need to assert scram_rst to reset the seed.

Hope that helps,
Evgeni