This question about “interleaved” CRC calculation comes up quite often. The short answer is – not quite. One problem is that you need to account for 128-bit of leading and trailing zeros when calculating CRC on split data:

data[255:0] = {data[255:128],128′b0} ^ {128′b0,data[127:0]}.

You can calculate CRC for each 128-bit chunk, but then you need to adjust the result by x^128 multiplication over finite field before proceeding to the next 256-bit data chunk.

Thanks,

Evgeni

Let say for example that we have a datapath of 256 bits. Is it possible to compute the first 128 bytes CRC and the second 128 bytes CRC at the same time, and then combine them (so without injecting the first result in the second computation)?

Thanks! ]]>

Thank you very much for the help!

The cookbook is also very useful.

Your website is wonderful and laid out very nicely. I will read the other parts of it as I get time, it looks very interesting.

-Stephen

]]>Yes, that’s the common practice.

Here is the reference you might find useful. See chapter 12 on page 89.

https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/manual/stx_cookbook.pdf

Thanks,

Evgeni

I understand your question. This is, in fact, one of the most frequently asked things. The simplest approach is to have 4 CRC generators for 32-, 64-, 96-, and 128-bit data. Then select the output based on the number of valid words. There are more complex solutions involving finite field arithmetics that help save some area. But I haven’t yet seen those in public domain. If I have some time, I’ll enhance this CRC generator. But it’s not a priority.

Thanks,

Evgeni

I have 32-bit words, arriving in a 128-bit bus, that I must generate a 32-bit CRC for. Each clock, the 128-bit bus will either have the 1st, the 1st two, the 1st three, or all four 32-bit words valid. I must add these 1 to 4 words to my 32-bit CRC in one clock. This repeats each clock until the end of data. How do I generate my 32-bit CRC given I have a varying (1 to 4) number of words to add each clock? Can I use a 128in-32out CRC generator and set the invalid words to zeros? Will this give the proper result (the zeroed words not affecting the CRC result)? OR can I use 4 32in-32out CRC generators, 1 on each lane of the 128-bit bus, and get 4 CRC sub-results and then combine them? Will this work; how to combine? OR is there another approach? Thank you so much for your advice! Great website BTW. ]]>

Each of the four streams will look like this: “….D000D000D000…”, where each nibble in that string is 32-bit. “D” is a data dword, followed by 3 dwords of zeros. So after each 32-bit CRC calculation on data, you’d need to multiply the result by X^96.

Thanks,

Evgeni

Can I use 4 32-bit CRC generators concurrently (1 for each of the 4 32-bit streams) and then combine the 4 CRC results at the end of the payload to form the complete CRC32 for the packet? Can the 4 partial results be easily combined?

Any suggestions would be much appreciated. Thanks.

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