Hi Evgeni,
Thank you for your good website and also good tools, keep it and grow it,
Dear Sir, i want to use “CRC32 for 802.3″ in my application, communication between PC and FPGA(in Verilog),
i use your CRC generator from “http://outputlogic.com/?page_id=321″ and choose “CRC32 for 802.3″, then i simulate it with this commands:

`timescale 1ns / 1ns

////////////////////////////////////////////////////////
//////////////// \ START TEST BENCH/ \\\\\\\\\\\\\\\\
////////////////////////////////////////////////////////

module TB__CRC32();

//———————————————————-
crc U_004__CRC32(
.data_in(Data_in),
.crc_en(Crc_en),
.crc_out(Crc_out),
.rst(rst_n),
.clk(clk)
);

wire [31:0]Crc_out;
reg Crc_en;
reg [7:0]Data_in;
//———————————————————-
reg clk;
reg rst_n;

initial // Initialize all variables
begin: TEST_CASE

rst_n = 0;
clk = 0;
Crc_en = 0;//disable
Data_in = 8′h41;//”A”

#10 @(negedge clk);
rst_n = 1;
#10 @(negedge clk);

rst_n = 0;
#10 @(negedge clk);

Data_in = 8′h41;//”A”
Crc_en = 0;//disable

#10 @(negedge clk);
Crc_en = 1;//enable
#1 @(negedge clk);
Crc_en = 0;//disable

#50 @(negedge clk);

#3000 @(negedge clk);
$finish; // Terminate simulation
end

always #1 clk = ~clk;

endmodule
////////////////////////////////////////////////////////
////////////////// \ END TEST BENCH/ \\\\\\\\\\\\\\\\
////////////////////////////////////////////////////////

OK, after this simulation and Data_in = 8′h41;//”A”
, Crc_out is: 32′h7e4fd274

>>>>BUT WHEN TEST IN PC SIDE

**1) i have my CRC32 module in C++ and my program
gets 8bit unsigned char data type
it calculate CRC32 with this polynomial
**0×04C11DB7 is the official polynomial used by PKZip, WinZip and Ethernet.
**x^32 + x^26 + x^23 + x^22 + x^16 + x^12 +
x^11 + x^10 + x^8 + x^7 + x^5 + x^4 + x^2 + x + 1
>>>>>>> i get for (character A) 8′h41 hex value this CRC32 value: 32′hd3d99e8b <<<<<<<<>>>>>> i get for (character A) 8′h41 hex value this CRC32 value: 32′hD3D99E8B <<<<<<<<>>>>>> i get for (character A) 8′h41 hex value this CRC32 value: 32′hd3d99e8b <<<<<<<<>verilog simulation say’s 32′h7e4fd274<>other calculations
say 32′hD3D99E8B<<, can you help me what is wrong here?
sorry if my question is very simple, but it is a big problem for me,

Thanks in advance,
Best Regards Serjik.

Hello Evgeni, I’m posting this message to check if it will be shown immediately. Because I already posted a message before.

Tennirva

Hi everyone,

i’m currently working on an hardware implementation of crc32 algorithm using the 2-step method, but it seems that the functions given in this paper by A. Simionescu: “CRC Tool: Computing CRC in Parallel for Ethernet,” Nobug Consulting,
are not doing fine.

If i’m not missunderstanding, here is he thing:

Using a polynomial’s degree of 123, each intermediate values of CRC calculated on each clock cycles with incoming words are on 123 bits. the initial value of CRC must be (others=>’0′) using this methode. The huge advantage of this way to compute CRC is that on last word, you don’t have to pay attention on empty bytes, because either you have 0 or 1 or 2 … empty bytes, if your word is filled with ‘0′ where it’s empty, your final CRC value will be the same.
=> Much less logical elements used.

But, what is weird with functions given on this article, is that the final value of CRC isn’t generated properly.

Does anyone implemented these functions and did it worked fine on first try ?

Thanks in advance,
Fabien

Here are the functions with issues:

function [31:0] next_crc32_data122;
input [122:0] inp;
integer i;
begin
for(i=0; i<123; i=i+1)
next_crc32_data122 = next_crc32_data1(32’h00000000, inp[122-i]);
end
endfunction

the function called in the loop is:

function [31:0] next_crc32_data1; //remainder of M(x)*x^32/P(x)
input [31:0] crc;
// previous CRC value
input B;
// input data bit (MSB first)
begin
next_crc32_data1 = {crc[30:0], 1’b0} ^ ({32{(crc[31]^B)}} &
32’b00000100110000010001110110110111);
end
endfunction

The first function with the loop may contain an error in it…

Regards,
Fabien

Hi, if any body needs “CRC32 for 802.3″ with equal results whith this sites crc32 generator,

http://crc32-checksum.waraxe.us/
or
http://www.lammertbies.nl/comm/info/crc-calculation.html

can use crc_chk.v and crc_gen.v files at this opensource project:
https://opencores.org/project,ethernet_tri_mode

Regards Serjik.

hi ,site is really great especially for beginner like me.can any one tell how the reg value lfsr_q linked with crc_out and also what abt its initial value.
thanks
DG

Hi,

The article is really useful. Thanks alot.

A little question. Why do we use ONE HOT values for the two matrices input ?

Regards

Thanks for reply — (I am nearly half way to the correct understanding)

Does it means that — it mimics the behaviour of LFSR in a sense that : There is only one input to a CRC and it matters only when it is SET (=1) — & since it is a shift register it shifts towards the output.

@Evgeni