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  1. August 26th, 2012 at 21:44 | #1

    Hi Dmitry,

    Yes, there is a typo.
    Swapping bits in 0×6522df69 will get 0×9add2096
    Swizzling all bits in 0×9add2096 will get 0×6904bb59

    Thanks,
    Evgeni

  2. Jamil
    November 7th, 2013 at 07:41 | #2

    CRC parallel calculation
    I have implemented a verilog code for CRC8 parallel with help of your document “A Practical Parallel CRC Generation Method”. For this many thanks.

    I do have a question regarding CRC polynomial: How can I insert the CRC polynomial (0x 107) as a parameter in my design? Is it possible?

    Thank you
    Jamil

  3. November 20th, 2013 at 06:49 | #3

    @Jamil

    Hi Jamil,

    One way to parametrize CRC polynomial is to do bitwise logic AND with the taps, for example, using “for” loop in Verilog.

    Thanks,
    Evgeni

  4. Kevin
    May 9th, 2014 at 07:21 | #4

    Hi Evgeni,
    I read you paper and understood the general idea of CRC parallel calculation, but not in depth. However, is it possible to implement the CRC parallel calculation using purely combinational logic (XOR arrary)? That is, if I load in the data and I can get the CRC checksum instantly. In the code generated by the website, it looks like the CRC of next block of data will depend on the CRC of previous block of data, which is not reasonable to me.
    Thanks for any help.
    Kevin

  5. May 9th, 2014 at 08:14 | #5

    Hi Kevin,

    This is the idea behind parallel CRC. The disadvantage of the parallel CRC is that it requires more XOR gates and more levels of logic as the data goes wider.
    It’s possible to implement, for example, 4096-bit CRC, and calculate it instantly on 4096-bit data. But in practice it’s implemented as 32-bit data (can be other value as well), and so it’d take 4096/32=128 clocks. That’s why there are registers on the output of the CRC to store intermediate results.

    Thanks,
    Evgeni

  6. Kevin
    May 9th, 2014 at 09:16 | #6

    @Evgeni
    OK, thanks. I am only using 8-13 bit data, so area is not a concern. If I want it calculated instantly, I just need to follow the method you described in paper and ignore the regs, right? In this case, I should just need to fix the signals which are used to be previous CRC state to all ‘1’s, right?

  7. May 9th, 2014 at 09:24 | #7

    Hi Kevin,

    That’s right. Most of the CRC specifications use ‘1’s to initialize the CRC. But strictly speaking, it doesn’t need to be the case.

    Thanks,
    Evgeni

  8. Kevin
    May 9th, 2014 at 09:39 | #8

    @Evgeni
    Thank you so much. I think I figured out the problem. Initialization with ‘1′ or ‘0′ may lead to different CRC checksum, but both of them are compliant to the same polynominal. In the standard arithmetic computation, we are used to putting ‘0′ when doing the long division, that’s the only difference in practical design.

  9. Denis
    July 3rd, 2014 at 02:25 | #9

    Hello. Your arcticle about CRC generator is very interesting. But replacement “for … loop” algorithm with “XOR” have advantage only for bad synthesizer like Xilinx. I use Altera Quartus for your example and two methods have the same result.
    Denis

  10. Terry Cornall
    August 27th, 2014 at 19:10 | #10

    Hi Evgeni
    Thanks very much for your article in outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf
    I found it very helpful in starting to grasp the concepts behind the design of parallel CRC generation.
    I did notice that maybe there is a typo on page 41 where you present a set of equations for Mout. I think the first line which is:
    Mout[0]=Min[1]^Min[1]^Min[0]^Min[3]
    should be
    Mout[0]=Min[1]^Min[1]^Nin[0]^Nin[3]

    Thanks again,
    Terry

  11. August 27th, 2014 at 20:57 | #11

    Hi Terry,

    That’s right, there is a typo. It was found a long time ago, here: http://outputlogic.com/?p=158#comment-8235

    Thanks,
    Evgeni

  12. Dick Karaus
    March 30th, 2015 at 04:10 | #12

    Has anyone tried the CRC for the CoaxPress standard? It is a 32bit CRC based on the IEEE_802.3. But, as noted in the standard, the input bits are reversed, the output crc is reversed, etc, etc. They give an example message packet in the standard and its computed CRC, but I can’t for the life of me get their CRC in their example. The standard is here and the example is on page 35 in the Comment. As they mention in the body of the text, the 8B/10B codes of K27.7 are treated as the D27.7 which is hex FB. They don’t exactly say what the input data length is, but I have tried 8bit, 16bit and 32bit inputs to no avail. I have tried negating the output crc….no good. If anyone has had success at this, please let me know. Thanks.

  13. March 30th, 2015 at 06:18 | #13

    Have you tried 1-bit data, all-zeros?

  14. Dick Karaus
    March 31st, 2015 at 04:07 | #14

    Evgeni,
    I’m not sure what you mean. I have been trying to recreate the example in the coaxpress standard so that I know my crc calculation code is correct. They give an example message with its calculated crc. It seems simple enough. I just can’t seem to recreate it.

  15. Dick Karaus
    March 31st, 2015 at 10:15 | #15

    I found my error. All is right with the world again.

  16. Frank Bruno
    July 17th, 2015 at 05:08 | #16

    Hi. Great site and really useful.
    I’m trying to generate a scrambler for 100GE. I am using a 640 bit bus w/ a 57 bit LSFR 1+x^38+x^57. I am getting the following error when it completes:

    Internal Server Error
    The server encountered an internal error or misconfiguration and was unable to complete your request.
    Please contact the server administrator, and inform them of the time the error occurred, and anything you might have done that may have caused the error.
    More information about this error may be available in the server error log.
    Additionally, a 404 Not Found error was encountered while trying to use an ErrorDocument to handle the request.

    Thanks,
    Frank

  17. July 17th, 2015 at 09:05 | #17

    Hi Frank,

    The time it takes to generate scrambler code grows quadratically with the number of data bits. Therefore, it’s quite possible that server times out. There is a command-line utility to generate CRC with wide data to overcome this kind of a problem. But unfortunately, I haven’t made public such a utility to generate scrambler code.

    Thanks,
    Evgeni

  18. shravan
    January 10th, 2016 at 21:23 | #18

    Hi

    In scrambler when we are giving input as all 0’s.then the generator giving output as all 0’s. but as per the scrambler defination long sequences can be changed with 0’s and 1’s.

    But in above case it is not effecting with all 0’s input.

    Can you please explain why it is not changing output with all 0’s input.

    Thanks,
    Shravan kumar

  19. shravan
    January 10th, 2016 at 22:09 | #19

    Hi Evgeni,

    Thanks for your response,
    As per your comments i tried with scrambler initial value with all 1’s and and scrambler input is all 0’s. then also its giving all 0’s output.because it it xor’ed with x^39+x^58(1 xor 1 =0) ,so 0(taps xor’ed) xor 0(input) output is 0. so it is not effecting by initial value(if the initial value like 10101010..seguence then it will effect).

    And iam using self synchronous scrambler(10gbase-R IEEE 802.3-2012_section4.pdf 49.2.6 scrambler)

    So can you please refer the above document.

    Thanks,
    Shravan kumar

  20. January 10th, 2016 at 22:40 | #20

    Hi Shravan,

    Seeding with all-1’s is just one option to implement a scrambler. Ethernet specification you’re referring to implements it differently to avoid the problem with long 0 sequences. The specification requires new scrambler seed for each packet. In addition, the data is NRZ and differentially encoded.

    Thanks,
    Evgeni

  21. John Vogel
    May 9th, 2016 at 14:22 | #21

    Hi Evgeni, I just wanted to thank you for this wonderful website. You totally rock!

    Best,
    John

  22. John Vogel
    May 10th, 2016 at 03:47 | #22

    Hi Evgeni, I want to understand how I can design a circuit, and variants of it with different polynomials, similar to the one your software produced ( scrambler module for data[31:0], lfsr[22:0]=1+x^2+x^5+x^8+x^16+x^21+x^23;); what paper or textbook would be the place to find the information? I want to understand the details of the math and algorithms that your software implemented, so that I can understnad and design the circuits myself.

    Thanks,
    John

  23. May 10th, 2016 at 10:54 | #23

    Hi John,

    You can start with this article:
    http://outputlogic.com/my-stuff/circuit-cellar-january-2010-crc.pdf

    It’s about CRC, but math used in scramblers is similar.

    Thanks,
    Evgeni

  24. sanjayy
    June 3rd, 2016 at 04:08 | #24

    Hi Evgeni,
    I was going through your paper “A Practical Parallel CRC Generation Method” at http://outputlogic.com/my-stuff/parallel_crc_generator_whitepaper.pdf
    and saw there is a typo in equation
    Mout[0]= Min[1] ^ Min[4] ^ Min[0] ^ Min[3] at page 43
    instead the equation should come out to be
    Mout[0]= Min[1] ^ Min[4] ^ Nin[0] ^ Nin[3]

    Can you please have a look at it.

    Thanks,
    sanjay

  25. June 3rd, 2016 at 06:59 | #25

    Hi Sanjay,

    Yes, it’s a known typo.

    Thanks,
    Evgeni

  26. Fenghua Feng
    August 3rd, 2016 at 05:25 | #26

    Hi Evgeni,

    Thank you so much for the wonderful tool. It’s really useful.

    I generated a verilog code for 16-bit CRC with polynomial X^16 + X^12 + X^5 + 1. The input data width is 16-bit. It seems that, in the verilog code, the input data is XORed with shift register bit by bit first, then the shift register shifts for 16 time, resulting the new shift register values for next cycle. Is this the standard generation process? I also see some methods that the input data is fed into the shift register bit by bit during the shifting operation. The results from two methods are different. I get confused which one I should use. If I use one method, and the receiver uses another, will it work correctly?

    Thanks,
    Fenghua

  27. Fenghua Feng
    August 3rd, 2016 at 11:03 | #27

    Hi Evgeni,

    I figured it out now. It seems that MSB first and LSB first will give different results.

    Thanks.
    Fenghua

  28. Daniyal Khurram
    August 7th, 2016 at 13:28 | #28

    Hi Evgeni,
    I just implemented your code to calculate CRC-6. I had the following question : Since the Parallel CRC generation method uses a serial CRC generator(called recursively) to calculate the H1 and H2 tables values which it then uses to come up with a refined parallel implementation, if I wanted to calculate the CRC register with the initial values set to all 0’s instead of 1’s as we are doing, can I just do so by setting the initial lfsr value to all 0’s during reset or would i need to calculate the table values again aswell and then come up with a XOR implementation using that?

  29. August 7th, 2016 at 20:27 | #29

    Hi Daniyal,

    H1 and H2 matrices are independent of the initial value of CRC.

    Thanks,
    Evgeni

  30. semo
    November 29th, 2016 at 05:46 | #30

    how we can generate pseudo – randonm number of length 79 by using lfsr

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