Hi Teruo,
The generators got broken after the latest round of site component updates. It’s fixed now.
The code is available here: https://opencores.org/projects/parallelcrcgen
Thanks,
Evgeni

@Evgeni
It looks like the LFSR generator is still/maybe newly broken, I get ‘Uncaught ReferenceError: pageTracker is not defined
at StartXHR (?page_id=275:386)
at HTMLInputElement.onclick (?page_id=275:485)’
after trying on a few different browsers it is the same.

Hello Evgeni.
In your paper “A Practical Parallel CRC Generation Method” in step 4 of building H1 matrix when I run my version of crc_parallel(N_in=0x1,M_in=0) I get 0 0 0 0 0 as the result instead of 0 0 1 0 1

My crc_parallel() calculates the checksum given N_in = message M_in = Polynomial. What am I missing?

I thought in CRC, feedback is based on polynomial and doesn’t depend the data width but I do see it changes for the same polynomial. Why is that? Also, on what basis the data bits XOR’ed as in which bits to XOR?

Hi Kumar,
In CRC, feedback depends on the data, I hope that part is clear. For parallel CRC with N data bits, the polynomial is updated N times in a single clock – that’s the whole point of having parallel CRC.

I used your tool to generate crc-32 with 64-bit/8-byte input

My question is
If unused bytes of the 8-byte input are not to be included for CRC generator, for example, byte-7 to byte-5 are not valid data, and byte-4 to byte-0 are valid data, what are the values for byte-7 to byte-5?

if this 5-byte data is the last data of the stream, can I use the crc-32 with 5-byte input to calculate the final CRC with the valid bytes (byte-4 to byte-9) AND the up-to-now result of the 8-byte crc-32 result as the initial value before this 5-byte input crc-32 calculation starts?

It has to be a different CRC to handle cases of misaligned or data with gaps. Setting unused or invalid data bytes to zero, for instance, will not work.

Other CRCs in the table have different polynomial and/or initialization value (FFs or zeros).
You can generate Verilog code by manually specifying desired polynomial. Then, in the generated code change initialization value (the default is FFs).

Hi Teruo,

The generators got broken after the latest round of site component updates. It’s fixed now.

The code is available here: https://opencores.org/projects/parallelcrcgen

Thanks,

Evgeni

@Evgeni

Thanks for the fix. Much appreciated! And thx also for the link to the code generators!!

@Evgeni

It looks like the LFSR generator is still/maybe newly broken, I get ‘Uncaught ReferenceError: pageTracker is not defined

at StartXHR (?page_id=275:386)

at HTMLInputElement.onclick (?page_id=275:485)’

after trying on a few different browsers it is the same.

Hello Evgeni.

In your paper “A Practical Parallel CRC Generation Method” in step 4 of building H1 matrix when I run my version of crc_parallel(N_in=0x1,M_in=0) I get 0 0 0 0 0 as the result instead of 0 0 1 0 1

My crc_parallel() calculates the checksum given N_in = message M_in = Polynomial. What am I missing?

I thought in CRC, feedback is based on polynomial and doesn’t depend the data width but I do see it changes for the same polynomial. Why is that? Also, on what basis the data bits XOR’ed as in which bits to XOR?

Hi Kumar,

In CRC, feedback depends on the data, I hope that part is clear. For parallel CRC with N data bits, the polynomial is updated N times in a single clock – that’s the whole point of having parallel CRC.

I a working on scramble of 8,16,32,64 bits by using the equation x16+x5+x4+x3+1.

I want descramble verilog code. Can you send me the same.

Hi Evgeni

Thank you for your useful tool.

I used your tool to generate crc-32 with 64-bit/8-byte input

My question is

If unused bytes of the 8-byte input are not to be included for CRC generator, for example, byte-7 to byte-5 are not valid data, and byte-4 to byte-0 are valid data, what are the values for byte-7 to byte-5?

if this 5-byte data is the last data of the stream, can I use the crc-32 with 5-byte input to calculate the final CRC with the valid bytes (byte-4 to byte-9) AND the up-to-now result of the 8-byte crc-32 result as the initial value before this 5-byte input crc-32 calculation starts?

Thanks a lot

Tony

Hi Evgeni

The code from your crc-32 verilog generator is based on one of the CRC-32 algorithm, or CRC-32/MPEG-2

The one in VQIP/Mentor used in real design is based upon CRC-32, not CRC-32/MPGE-2

Please refer to https://crccalc.com for different CRC-32 algorithms

Can you advise how to use your tool to generate Verilog code of CRC-32 algorithm, not of crc-32/mpeg-2 as your tool does now?

Thanks

Tony

Hi Tony,

It has to be a different CRC to handle cases of misaligned or data with gaps. Setting unused or invalid data bytes to zero, for instance, will not work.

Thanks,

Evgeni

Hi Tony,

Other CRCs in the table have different polynomial and/or initialization value (FFs or zeros).

You can generate Verilog code by manually specifying desired polynomial. Then, in the generated code change initialization value (the default is FFs).

Thanks,

Evgeni

@Arun Kumar

i also required same