LFSR Counters – Part 3
Here is how the LFSR Counter Generator works:
(1) Specify counter value, e.g. 200. It’s 8 bits, so the tool selects 8-bit LFSR with polynomial coefficients taken from the table in [1].
(2) Reset LFSR to 0, run a loop that shifts the LFSR 200 times. Then latch its value (LFSR_COUNT_VAL).
(3) Use that 8-bit LFSR and LFSR_COUNT_VAL to generate a Verilog code. When the LFSR hits LFSR_COUNT_VAL, it counted 200.
This approach is working because the polynomial selected in (1) has a maximum-length property. That is it generates a sequence of unique values from 0 to 2n-1.
I synthesized a 32-bit LFSR counter for Xilinx Virtex5 chip and compared its size with a regular 32-bit counter.
Here are the results:
| Module | Slices | Regs | LUTs |
| regular_counter | 17 | 32 | 44 |
| lfsr_counter | 10 | 32 | 7 |
References
- Peter Alfke, Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators, Xilinx application note Xapp052
