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LFSR Counters – Part 3

  Here is how the LFSR Counter Generator works:

(1) Specify counter value, e.g. 200. It’s 8 bits, so the tool selects 8-bit LFSR with polynomial coefficients taken from the table in [1].

(2) Reset LFSR to 0, run a loop that shifts the LFSR 200 times. Then latch its value (LFSR_COUNT_VAL).

(3) Use that 8-bit LFSR and LFSR_COUNT_VAL to generate a Verilog code. When the LFSR hits LFSR_COUNT_VAL, it counted 200.

This approach is working because the polynomial selected in (1) has a maximum-length property. That is it generates a sequence of unique values from 0 to 2n-1.

I synthesized a 32-bit LFSR counter for Xilinx Virtex5 chip  and compared its size with a regular 32-bit counter.

Here are the results:

Module Slices Regs LUTs
regular_counter 17 32 44
lfsr_counter 10 32 7


  1. Peter Alfke, Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators, Xilinx application note Xapp052

  1. June 30th, 2011 at 05:17 | #1

    You may also find this article interesting.
    On Arbitrary Cycle n-Bit LFSRs http://www.fpgacpu.org/usenet/lfsrs.html

    I also published an LFSR generator. It is in the XSOC/xr16 kit, lfsr.c, at http://wwww.fpgacpu.org/xsoc/xsoc-beta-093.zip .

  2. June 30th, 2011 at 09:45 | #2

    Hi Jan,

    Thanks for the link. Interesting approach to generate 2^n cycle counters.


  3. Michael
    December 16th, 2011 at 11:12 | #3

    Great side, thanks!
    I wondered is there a good way to convert a LFSR counter to a normal counter without using a huge lookup-table? I would like to use a 20bit LFSR counter to count pulses, and then after some time read the LFSR and decode it to a binary counter number. The brute-force approach would be to use block ram as a look up table with the LFSR being the address and the 20bit entry the counter value. Do you maybe know a better way?

  4. December 16th, 2011 at 20:14 | #4

    Hi Michael,

    No, I’m not aware of a good way to map LFSR to a binary.


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