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  1. AG
    June 17th, 2009 at 14:36 | #1

    Eng. Evgeni Stavinov

    I was reading your PDF about “Parallel CRC Generation Method” and is very interesting, about this theme I developed a routine to calculate the CRC of packets from the net but I have a doub about this and I know that you are an expert in FPGA programation and for that reason me I ask to you the next.

    I´m working with “Started Kit Board Spartan3E” develop a ethernet comunication and now I´m receiving packet from the net

    I have a program on VHDL language which calculate the “CRC32” of a packet from ethernet and it do it fine, I know that because I check the packet I received from the ethernet port with other software that calculate the CRC32(HashCalc) and the result it´s the same, and like a third instance I do the same operation on a web-page that can calculate CRC32 on-line.

    All is good to this point, but the problem is with the “CRC32” that comes with the packet from ethernet, it not correspond with the “CRC32” of my program and in accordingly neither with the “CRC32” from the other softwares.

    I don´t know how can occur this, I don´t understand what it´s happend, in theory my “CRC” it´s good but no correspons with the “CRC” of the packet.

    Could you said me why is occurring this?, exist some diference between the theory an the practice.

    I´m going to present you the packet and CRC´s.

    Packet from the net. (HEX).

    Zeros that my program add to the end of packet to calculate the CRC, rule of the theory, 4 bytes (HEX).

    “CRC” from my program and others softwares. (HEX).

    “CRC” of the packet from the net.

    Could you see the diference?, I think it´s other operation at the end of the calculate of the “CRC” which make the diference, something that in theory don´t said, I don´t know.

    I appreciate very much that you could explain me why this phenomenon.

    Thank you very much in advance and I hope for your answer.


  2. June 17th, 2009 at 15:34 | #2

    Dear AG,
    Thanks for taking your time to read my CRC article.
    Regarding your question, it’s hard for me to provide an intelligent answer to why you don’t get the same results for received CRC without looking into the implementation.

  3. Mark Owen
    October 27th, 2009 at 11:36 | #3

    Is it possible to compute a case where the data width is >2000? I noticed the limit on 1024. I am looking at the parity equation of x32 + x30 + x21 + x9 + 1 and would like to use a data size of 2080. The parity width is 32. Thanks!

  4. October 27th, 2009 at 12:09 | #4

    Hi Mark.

    Are you using CRC Generator ?

    You can download a stand-alone application from
    It doesn’t have this limitation on a data size.


  5. Mark Owen
    October 27th, 2009 at 12:17 | #5


    No, I was using the Scrambler generator. Perhaps I will give the crc-gen-verilog tool a try – thanks!


  6. J.J. Barrow
    October 29th, 2009 at 16:08 | #6

    Hello Evgeni,

    I’m using the Parallel Scrambler tool to produce an x8 version of the scrambling function used for Digital Video Broadcasting (DVB-S2). This scrambler is used as an example on Wikipedia for the discussion of scramblers and is found here:

    Upon implementation of this I see an inconsistency between the parameters I need to enter for the logic generation tool, and what the DVB-S2 Specification (ETSI EN 302 307) presents as the function definition. In particular the specification (and wikipedia) say the function is 1 + X(14) + X(15). (with an initialization of 100101010000000).

    So with LFSR width of 15, which I provide the tool, ‘step2’ provides 1 + x(1) … x(14) and stops, there is no x(15). Hmmm. Perhaps there is a descrepency with x(0) and how this is treated, can you provide insight? For instance it appears maybe the ETSI spec. itself is incorrect? and should be 1 + X(13) + X(14). Or is the logic gen. tool off by one?

    Thank You,

  7. October 30th, 2009 at 02:23 | #7

    Hi J.J.,

    For a 15-bit wide polynomial there are 15 check boxes from x^0, which is 1, to x^14. x^15 is a feedback, so it’s always there.
    So for “1 + X(14) + X(15)” you select boxes 1 and x^14.
    I agree that it’s somewhat confusing, and I probably should add a grayed-out x^15 check box.


  8. March 3rd, 2010 at 10:36 | #8

    I can see that it been a while since anyone have replyed or posted on this site.
    So is it still monitored? and is it still possible to ask question. I have on in regard to the scrambler generator.

    But i wont start explaning my problem, since it will take time, and it whould be a waste if noone will answer it anyway

    Regards Vinther.

  9. March 3rd, 2010 at 12:36 | #9

    Hi Vinther,

    I’ll try to answer your question.


  10. Kaitlin
    April 3rd, 2010 at 00:41 | #10

    Hi Evgeni,
    Could you supply Paraller Descrambler Generator similar to Paraller Scrambler Generator ?


  11. Martin
    June 14th, 2010 at 10:25 | #11

    Hello, thank you for publishing the code of the parallel scrambler.
    I want to use the scrambler with a 16 bit interface where the two bytes should be
    scrambled or passed through.
    In this way could you give me a hint how to add two scram_en bits to implement this?
    A not scrambled byte shall also reset the scrambler to the seed.

  12. June 14th, 2010 at 12:23 | #12

    Hi Martin,

    You can add pass_thru input, and change the logic to:

    data_out <= pass_thru ? data_in : (scram_en ? data_c : data_out);

    You'd need to assert scram_rst to reset the seed.

    Hope that helps,

  13. Martin
    June 22nd, 2010 at 10:02 | #13

    Hello Evgeni,
    thank you for the hint,
    it looks that with pass through the input will lead to the output and the lfsr_q will stall.
    But how to pass through the upper 8 bits of a 16 bit bus while scrambling the lower ones or vice versa?
    In this way IMO when the upper bits are used only these bits must be XORed to the lfsr and based on which or both bytes are passed through there should be 3 different lfsr_c vectors which are used to update the lfsr_q at the next clock edge.
    Or is it much simpler but I haven’t recognized it?

    BR, Martin

  14. June 23rd, 2010 at 11:47 | #14

    You can have, for example:
    data_out < = scram_en ? {data_in[15:8], data_c[7:0]}: data_out);

  15. al b.
    October 26th, 2010 at 13:33 | #15

    Hello Evgeni,

    Great website..thank you! here is my question: I used your scrambler generator to generate the verilog code for the OTN scrambler ( 1+ X + X^3 + X^12 + X^16). my input is 64 bit wide. to make things simpler, I started with a 16 bit wide data in (of course after I generated a 16 bit scrambler using your tools). However, when I compared the output generated from your tools to the xilinx XAP651,(xilinx has a not synthesizable 16bit otn scrambler the outputs looked different. for example, my calculation shows that the first 2 output data should be 5432 then E55C which is also what I got using xilinx scrambler. but with the 16 bit scrambler generated using your tools the firtst 2 output were C4C2 then 5752. any ideas why I am getting a different result?


  16. October 26th, 2010 at 14:35 | #16


    There are several reasons for the mismatch. Some of them are:
    – bit order into serial scrambler is not the same as how the data is fed into the parallel scrambler
    – input data bits are inverted
    – LFSR is not initialized the same way. A lot of protocols initialize it with F-s, and that’s what is done in the parallel scrambler.

    A good place to start troubleshooting is to generate a serial scrambler with the same polynomial and data width=1, and make sure that it matches the reference.


  17. al b.
    October 27th, 2010 at 12:12 | #17

    Hello Evgeni and thank you for your quick reply. here is my testbench that I used to test the 16 bit scrambler mentioned above.
    @ (posedge clk)
    scr16_data_in = 16’habcd;
    scram_rst = 1;
    scram_en = 0;
    @ (posedge clk)
    scram_en = 1;
    scram_rst = 0;

    as you can see my input data is 16’habcd. but I am still geting C4C2 followed by 5752 at the output where I am expecting to see 5432 folowed by E55C. if the generated code is correct, then the problem must be in the testbench. therefore, could you please take a look at my testbench and let me know what am I doing wrong?

    Thank you,

  18. October 27th, 2010 at 13:24 | #18


    I found xapp651.pdf, but not with the code example. Can you send me the link?
    On Figure 2 there is a scrambler description. I’m not sure you’re using the right polynomial. There are two notations: Fibonacci and Galois. The generator on this site is using Galois, but there is a simple conversion.
    There are few posts on that here.


  19. al b.
    October 27th, 2010 at 14:04 | #19


    Hello Evgeni,

    Here is the link for you can also access the link from xapp651.pdf page 4.

    Here is also the link for the OTN spec. you can see the polynomial in section 10.1 page 34 and 35.

    thanks for your help,

  20. October 28th, 2010 at 08:05 | #20


    I looked at the specs. LFSR polynomial for the scrambler is in Fibonacci notation. My algorithm is in Galois notation, which is what most scramblers are using. Both are equivalent, and there is a conversion process from Fibonacci to Galois, which involves reversing the taps and finding the right init value (it’s not all-FFs anymore). My algorithm should work with the Fibonacci, but it’ll require some changes.
    You can also change the code in xapp651 to 64-bit. It should synthesize, although it can produce bigger design comparing with the “native” implementation with XOR trees.


  21. Al
    October 28th, 2010 at 12:37 | #21

    Great job! and thank you very much for clarifying that. Now I just have to find out how to convert your algorithm from Galois to Fibonacci. I am a little tight on gates.

    Thansk again,

  22. December 5th, 2010 at 21:28 | #22


    thanks for given verilog code on scrambler . can u give verilog code for error correcting code like bch & reed solomon code



  23. Muda
    January 26th, 2011 at 10:03 | #23


    that are very nice tools!
    I generated a scrambler with the function “1 + X(4) + X(9)” in vhdl and now I need a descrambler for it.
    Is another tool planned for descramblers? or what changes do I need to get a descrambler from that scrambler?


  24. January 26th, 2011 at 10:16 | #24

    Hi Muda,

    In most cases descrambler has the same logic as scrambler. There is some more discussion on this topic here:


  25. sagar
    February 15th, 2011 at 23:12 | #25

    sir i am not getting what is lfsr_q variable in the CRC code for polynamial x^16+x^12+x^5+1

  26. February 16th, 2011 at 07:00 | #26


    lfsr_q variable starts with all F-s (or other initial value) upon reset. Then, the next value is recalculated every clock depending on the input data and its current value. At the end it contains the CRC.


  27. singh sarvesh
    April 25th, 2011 at 10:23 | #27

    hey…………i require scrambler n desrambler vhdl code together….can i get it here????

  28. April 25th, 2011 at 13:00 | #28


    In most cases the code for scrambler and descrambler is the same, if that’s what you’re asking.


  29. imtiaz ahmed kkhan
    August 5th, 2011 at 03:11 | #29

    dear Sir,

    A) i am a student of underwater communication system. I want to know how to calculate error detection rate in CRC for different pay load…like 1 byte CRC Vr 2 byte CRC…….how we calculate the actual CRC degree for 23 byte CRC..

    B)my 2nd question the what is the consedering point for the N byte CRC……
    please help me…My professor is very angry…….I have only 2 more days………any information….

  30. August 5th, 2011 at 03:26 | #30


    Perhaps this article on parallel CRC generation might be of help.


  31. imtiaz ahmed kkhan
    August 7th, 2011 at 19:16 | #31

    dear sir , thank you for your kind consederation….and quick replay….now i know how to crc work.

    I want to know the how to calculate the “error detection rate” for different CRC degree. to compare the ideal crc with fix payload size.. example : when i have payload size fix 12byte. CRC-8 or CRC-16 , If CRC-16, why CRC-16 ? calculate error detection rate of differeent CRC ….. if CRC-8 good enough for 12byte, why i use CRC-16 ?

    different between parallel CRC and SERIAL CRC

  32. August 7th, 2011 at 20:00 | #32


    Here is a good introductory article on CRC error detection properties:
    To put it simple, CRC is a remainder from division of data by CRC polynomial. The longer the CRC polynomial, the lesser chance that two or more different data values will result in the same CRC.

    Serial CRC has a 1-bit data input. Parallel CRC can calculate CRC on several data bits at a time, which is faster. So, for example, it’d take 12*8=96 clocks to calculate CRC of 12-byte data using serial approach. It’d take only 3 clocks to do the same using 32-bit parallel CRC.


  33. imtiaz ahmed kkhan
    August 31st, 2011 at 21:13 | #33

    when i use the CRC in underwater communication Then i had the CRC error 7 to 12 time , one time CRC error. use CRC-8, is it change if we use CRC-16….error detecton rate is important …better rate ?

  34. joe
    September 6th, 2011 at 08:26 | #34

    Nice site. But the result seems wrong, I got same problem as other posted here, and compared with other standard CRC result, and other paper, for example:

  35. joe
    September 6th, 2011 at 10:22 | #35

    I use as per Evgeni suggested the code to generate crc32 .v, the result is different than what I get here. It’d would be appreciated if Evgeni can help.

  36. Babar
    January 27th, 2012 at 10:06 | #36

    Can anybody give me some precious words about scrambling?
    How scrambling avoids EMI??

    Thanks in advance

  37. January 27th, 2012 at 11:22 | #37

    Hi Babar,

    Scrambling randomizes data. That removes high-frequency zero-one transitions and repetitive patterns, which in turn reduces EMI.


  38. Babar
    January 30th, 2012 at 05:30 | #38

    Thanks a lot Evgeni.


  39. Dominique
    February 22nd, 2012 at 07:30 | #39


    I have designed in VHDL an parallel CRC generator on 32 bits that work well. I would like also compute the CRC with a message that is not multiple of 32 bits (last word of message can contains 1, 2, 3 bytes only). How is it possible to do this computation?

  40. February 22nd, 2012 at 08:12 | #40


    This technique is known as “byte-enable parallel CRC”. Here is one paper that describes it:


  41. Ramu.37
    March 6th, 2012 at 05:56 | #41

    I have designed a parallel Ethernet CRC generator (data width=64). It is working fine with messages that are integer multiples of 64bits. what i should do if the last word is less than 64 bits. I have studied link #40, but i am searching for a single step solution. is it possible?

  42. March 6th, 2012 at 08:12 | #42


    One approach is to have another CRC generator for each message that is not 64-bit.


  43. Ramu.37
    March 6th, 2012 at 18:24 | #43

    thanks for the reply.
    In this case i may require 7 crc generators (data width = 8) extra with original crc generator (data width = 64). this will increase my area consumption.
    what if i use 8 crc generators (data width = 8) complete my job as following:
    crc_c1 <= crc32 (crc_c8, data_in (63 downto 56)) ;
    crc_c2 <= crc32 (crc_c1, data_in (55 downto 48)) ;
    crc_c3 <= crc32 (crc_c2, data_in (47 downto 40)) ;
    crc_c4 <= crc32 (crc_c3, data_in (39 downto 32)) ;
    crc_c5 <= crc32 (crc_c4, data_in (31 downto 24)) ;
    crc_c6 <= crc32 (crc_c5, data_in (23 downto 16)) ;
    crc_c7 <= crc32 (crc_c6, data_in (15 downto 8)) ;
    crc_c8 <= crc32 (crc_c7, data_in (7 downto 0)) ;

    crc32 is a function which performs crc32 generation (data width = 8).

    is it going to effect my timing?

  44. March 6th, 2012 at 19:50 | #44

    This will take 7 clocks to complete CRC for that 56-bit data chunk. If you data arrival rate is faster, this approach is not going to work.


  45. James Brakefield
    May 1st, 2012 at 17:41 | #45

    Chapter 36 on FPGA configuration:
    Actel (now Microsemi) is the main vendor currently using anti-fuse (RTAX series).
    Quicklogic has something similar called ViaLink (PolarPro series).
    At one time Cypress and Xilinx had anti-fuse parts.
    Actel(Fusion, others), Lattice(MachXO2 & XP2), Altera(MAX series) and Xilinx (coolrunner, xc9500) use on-chip reprogrammable flash as configuration memory.
    E.g., there are three kinds of FPGAs: SRAM based, flash based and anti-fuse.

  46. May 2nd, 2012 at 06:03 | #46

    Thanks for the comment.

  47. Jx
    July 19th, 2012 at 14:56 | #47

    Hi Evgeni,

    I encounter a problem on the CRC32 generated code using your crc verilog generator, with 64 bits data input.

    So, my hardware implementation has 64 bits data width parallel CRC32 computation, and I have a 8 bits data width CRC32 software to verify the data.

    Let say my first input data is 0x0000_0000_0000_0000 for the 64-bits data width hardware, and I will assume that 8 cycles of 0x00 into my 8 bits data width software will generate the same result. Both of them have initial CRC value 0xFFFFFFFF.

    The outcome of the hardware is 0x6904bb59, while the software is 0x6522df69. The reason I choose all 0’s number to verify is to avoid input sequence problem. So, this result puzzles me a little. Shouldn’t a 64-bits data width CRC32 be equivalent to 8 cycles of 8-bits data width CRC32?

    Also, I change my hardware to use 8-bits data width, it is still not matching with the software. The sample software CRC calculator I use is in with hex input.

    I am looking forward for your reply, and thanks for the great website and help.


  48. July 19th, 2012 at 15:56 | #48


    That’s interesting.
    If you take 0×6522df69 and swap the bits from 0 to 1 and 1 to 0, you’d get 0x9a44b096.
    Then if you take 0x9a44b096 and swizzle all 32 bits, you’d get 0×6904bb59.
    So, somebody is doing extra bit swapping and swizzling.


  49. Jx
    July 20th, 2012 at 07:59 | #49

    Hi Evgeni,

    Thanks for the quick reply, it is a very good hint that both piece of logics are working correctly, just output in different format. Now I just have to find a way to match the both.


  50. Dmitry
    August 25th, 2012 at 12:25 | #50

    Hi Evgeni,
    I don’t understand how to get 0×9a44b096 from 0×6522df69. If I’ll change bits from 0 to 1 and 1 to 0 I’ll get 0x9ADD2069.
    Could you explain what you mean?

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