Please leave your comments

  1. August 23rd, 2020 at 22:42 | #1

    Hi Teruo,
    The generators got broken after the latest round of site component updates. It’s fixed now.
    The code is available here:

  2. Teruo Utsumi
    August 27th, 2020 at 23:12 | #2

    Thanks for the fix. Much appreciated! And thx also for the link to the code generators!!

  3. Nathan Francque
    January 28th, 2021 at 04:48 | #3

    It looks like the LFSR generator is still/maybe newly broken, I get ‘Uncaught ReferenceError: pageTracker is not defined
    at StartXHR (?page_id=275:386)
    at HTMLInputElement.onclick (?page_id=275:485)’
    after trying on a few different browsers it is the same.

  4. Tich
    July 27th, 2021 at 13:57 | #4

    Hello Evgeni.
    In your paper “A Practical Parallel CRC Generation Method” in step 4 of building H1 matrix when I run my version of crc_parallel(N_in=0x1,M_in=0) I get 0 0 0 0 0 as the result instead of 0 0 1 0 1

    My crc_parallel() calculates the checksum given N_in = message M_in = Polynomial. What am I missing?

  5. kumar
    September 15th, 2021 at 13:28 | #5

    I thought in CRC, feedback is based on polynomial and doesn’t depend the data width but I do see it changes for the same polynomial. Why is that? Also, on what basis the data bits XOR’ed as in which bits to XOR?

  6. September 15th, 2021 at 16:02 | #6

    Hi Kumar,
    In CRC, feedback depends on the data, I hope that part is clear. For parallel CRC with N data bits, the polynomial is updated N times in a single clock – that’s the whole point of having parallel CRC.

  7. Arun Kumar
    September 25th, 2021 at 06:57 | #7

    I a working on scramble of 8,16,32,64 bits by using the equation x16+x5+x4+x3+1.

    I want descramble verilog code. Can you send me the same.

  8. Tony Luan
    October 25th, 2022 at 15:51 | #8

    Hi Evgeni

    Thank you for your useful tool.

    I used your tool to generate crc-32 with 64-bit/8-byte input

    My question is
    If unused bytes of the 8-byte input are not to be included for CRC generator, for example, byte-7 to byte-5 are not valid data, and byte-4 to byte-0 are valid data, what are the values for byte-7 to byte-5?

    if this 5-byte data is the last data of the stream, can I use the crc-32 with 5-byte input to calculate the final CRC with the valid bytes (byte-4 to byte-9) AND the up-to-now result of the 8-byte crc-32 result as the initial value before this 5-byte input crc-32 calculation starts?

    Thanks a lot

  9. Tony Luan
    October 26th, 2022 at 09:34 | #9

    Hi Evgeni

    The code from your crc-32 verilog generator is based on one of the CRC-32 algorithm, or CRC-32/MPEG-2

    The one in VQIP/Mentor used in real design is based upon CRC-32, not CRC-32/MPGE-2

    Please refer to for different CRC-32 algorithms

    Can you advise how to use your tool to generate Verilog code of CRC-32 algorithm, not of crc-32/mpeg-2 as your tool does now?


  10. October 27th, 2022 at 01:27 | #10

    Hi Tony,

    It has to be a different CRC to handle cases of misaligned or data with gaps. Setting unused or invalid data bytes to zero, for instance, will not work.


  11. October 27th, 2022 at 01:31 | #11

    Hi Tony,

    Other CRCs in the table have different polynomial and/or initialization value (FFs or zeros).
    You can generate Verilog code by manually specifying desired polynomial. Then, in the generated code change initialization value (the default is FFs).


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