There is a long list of things that can go wrong during CRC calculation. I’d need more information to help you.

Thanks,
Evgeni

ENTITY TL_CRC_32 IS

PORT (
clk : IN STD_LOGIC; — clock
reset : IN STD_LOGIC; — asynchronous reset
crc32_init : IN STD_LOGIC; — set CRC register to initial value
crc32_enable : IN STD_LOGIC; — enable CRC calculation
serial_IN : IN STD_LOGIC; — serial input data
crc32 : OUT bus32); — CRC32 accumolator

END ENTITY TL_CRC_32;

ARCHITECTURE behaviour OF TL_CRC_32 IS

SIGNAL crc32_shifter : STD_LOGIC_VECTOR (31 DOWNTO 0);
–SIGNAL temp : STD_LOGIC_VECTOR (31 DOWNTO 0);
SUBTYPE poly_vector IS BIT_VECTOR (31 DOWNTO 0);
CONSTANT poly : poly_vector := X”04C11DB7″; — polynominal
CONSTANT initval : STD_LOGIC := ‘1′; — initial crc reg. value

BEGIN

shift_data : PROCESS (clk, reset) IS
BEGIN
IF reset = ‘0′ THEN
crc32_shifter initval);
ELSIF clk’EVENT AND clk = ‘1′ THEN
IF crc32_init = ‘1′ THEN — load crc reg with init value
crc32_shifter initval);
ELSIF (crc32_enable = ‘1′) THEN — serial crc bit calculation
FOR i IN 0 TO 31 LOOP
IF (poly(i) = ‘1′) THEN
IF (i = 0) THEN
crc32_shifter(0) <= serial_IN XOR crc32_shifter(31);
ELSE
crc32_shifter(i) <= crc32_shifter(i-1) XOR serial_IN XOR crc32_shifter(31);
END IF;
ELSE
crc32_shifter(i) <= crc32_shifter(i-1);
END IF;
END LOOP;
END IF;
END IF;
END PROCESS shift_data;

crc32 <= crc32_shifter;

END ARCHITECTURE behaviour;

Can you please help me?

The method should work with either Fibonacci or Galois LFSRs. I expect that both will produce the same result – matrix coefficients, or XOR tree – but will need to work out a formal proof for that claim.

Thanks,
Evgeni

Im not completly clear if that answer is a yes or no . However, i know that the XOR trees are not a LFSR. My question, dont know if i have been unclear, is that the matrixes you use to calculate thoes XOR tress are based on a calculation made over a software implementation of a Galois LFSR. My question is will the same method work if the Matrix is made by a software implemented Fibonacci LFSR insted ?

Galois and Fibonacci notations are used to describe linear feedback shift registers, which are used for CRC with 1-bit data.
Parallel CRC in my method is using XOR trees, which is a structure different from LFSR. It reduces to Galois-style LFSR for 1-bit data.

Thanks,
Evgeni

A quick question, I’ve just read your PDF “circuit-cellar-january-2010-crc.pdf”. And you’ve explained to me privously that you use Galois notation.

At the step where you generate the matrixes with your software LFSR implementation, which i guess is implemented with Galois notation. Is it possible to use a Fibonacci notation insted?
And will the reset of the proceedure still hold ?

I think a good place to start with understanding a 1-bit CRC is on wiki: http://en.wikipedia.org/wiki/Cyclic_redundancy_check

Thanks,
Evgeni

I am trying to understand CRC generation using the shift register, could someone help to explain how it works, thanks.

regards
Essennell

I worked with CRC32 and datawidth=256 bit that run at 133MHz on Virtex4. I’d expect your configuration to meet timing. But before you resort to pipelining, I’d recommend trying to floorplan it.

Thanks,
Evgeni